Shift-BNN: Highly-Efficient Probabilistic Bayesian Neural Network Training via Memory-Friendly Pattern Retrieving
Published in IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021
Primary contributor to the Verilog HDL implementation and FPGA-based evaluation (resource/energy estimation) of the proposed hardware accelerator. Designed a hardware architecture for efficient BNN training on edge and server systems.
Recommended citation: Qiyu Wan, Haojun Xia, Xingyao Zhang, Lening Wang, Shuaiwen Leon Song, Xin Fu. "Shift-BNN: Highly-Efficient Probabilistic Bayesian Neural Network Training via Memory-Friendly Pattern Retrieving." In Proceedings of the 54th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021.
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